1. Field of the Invention
The instant disclosure relates to an amplifier; in particular, to a buffer circuit having a plurality of amplifiers.
2. Description of Related Art
Please refer to FIG. 1A, FIG. 1B and FIG. 1C respectively showing a schematic diagram of an application for a conventional buffer circuit.
Please refer to FIG. 1A, FIG. 1B and FIG. 1C respectively showing a schematic diagram of an application for a conventional buffer circuit. The buffer circuit can be implemented by one or a plurality of operational amplifiers. As shown in FIG. 1A, the conventional buffer circuit 1 is implemented by an integrated circuit (IC) comprising two operational amplifiers OP1 and OP2. Each operational amplifier has a non-inverting input terminal (+), an inverting input terminal (−) and an output terminal (Vout1 or Vout2). The inverting input terminal (−) of the operational amplifier OP1 is connected with the output terminal Vout1, thus the operational amplifier OP1 forms a buffer. Similarly, the inverting input terminal (−) of the operational amplifier OP2 is connected with the output terminal Vout2, thus the operational amplifier OP2 forms a buffer. The non-inverting input terminal (+) of the operational amplifier OP1 is connected with the input terminal Vin1 (an input pin, for example) of the package 10, and non-inverting input terminal (+) of the operational amplifier OP2 is connected to the input terminal Vin2 of the package 10. As shown in FIG. 1A, the operational amplifiers OP1 and OP2 forming the buffer circuits operate independently. When electricity is not provided to the operational amplifiers OP1 and OP2 for disabling the operational amplifiers OP1 and OP2, the output terminal Vout1 of the operational amplifier OP1 and the output terminal Vout2 of the operational amplifier OP2 can be connected (or biased) to a biasing voltage. As shown in FIG. 1C, the output terminal Vout1 of the operational amplifier OP1 is exemplarily connected to the supply voltage PW, and the output terminal Vout2 of the operational amplifier OP2 is exemplarily connected to the ground GND.
However, in order to make the buffer circuit provide larger drive ability, a plurality of buffer circuits can be connected in parallel. For the application shown in FIG. 1B, the input terminal Vin1 connected with the operational amplifier OP1 and the input terminal Vin2 connected with the operational amplifier OP2 are shorted (or so called “common” to be the input terminal Vin), and the output terminal Vout1 of the operational amplifier OP1 and the output terminal Vout2 of the operational amplifier OP2 are common for being the output terminal Vout. However, the offset voltage of each operational amplifier may be different. As shown in FIG. 2, the operational amplifier OP1 has an offset voltage Vos1, the operational amplifier OP2 has an offset voltage Vos2, such that the voltage level of the output terminal Vout1 of the operational amplifier OP1 may be different from the voltage level of the output terminal Vout2 of the operational amplifier OP2. Therefore, a leakage current IL may occur between the output terminal Vout1 and the output terminal Vout2, wherein the shown transistor in the operational amplifier is the output stage of the operational amplifier.